1. Field of the Invention
The present invention relates to a semiconductor memory having a memory cell with a single-ended digit structure that reads data over a single digit line.
2. Description of Related Art
A semiconductor memory having a memory cell with a single-ended digit structure, as shown in FIG. 10, for example, is widely known. Japanese Unexamined Patent Application Publication No. 03-73493 (FIG. 2), for example, describes this kind of semiconductor memory.
The semiconductor memory 100 shown in FIG. 10 is Static Random Access Memory (SRAM). The semiconductor memory 100 has memory cells 101 arranged in an array composed of the n-number of rows and the m-number of columns (n and m are each positive integers of 2 and above), with n×m bits, and a word line driver circuit 102. Write word lines 103 and read word lines 104, each of the same number as rows (n-number), are derived from the word line driver circuit 102. The in-number of read/write shared digit lines 105 are formed, one for each column, and a column selector 106 for selecting one from the digit lines 105 to read or write data. Signal lines 107 are derived from the column selector 106 for transmitting a data write signal to selected memory cells 101 to which data is to be written and a data read signal (digit voltage) from selected memory cells 101 from which data is to be read. A column select signal driver circuit 108 outputs a column select signal to the column selector 106. To transmit the column select signal to the column selector 106, signal lines 109 of the same number as columns (m-number) are derived from the column select signal driver circuit 108. The semiconductor memory 100 further has the n-number of dummy cells 110, placed one for each row, for generating a reference voltage. A dummy digit line 111 is commonly connected to the source terminal of an access transistor 1101 of each dummy cell 110. The dummy digit line 111 and the signal line 107 are both connected to a complementary level comparing sense amplifier and data write buffer combined circuit 112.
Each read word line 104 is commonly connected, in each row, to the gate terminal of an access transistor 1011 of each of the memory cells 101 and also to the gate terminal of the access transistor 1101 of each of the dummy cells 110.
Each write word line 103 is commonly connected, in each row, to the gate terminal of a write address selection switch transistor 1012 of each of the memory cells 101.
Each digit line 105 is commonly connected, in each column, to the source terminal of the access transistor 1011 of each of the memory cells 101 and also to the drain terminal of the write address selection switch transistor 1012 of each of the memory cells 101.
When the semiconductor memory 100 having this structure reads data from the memory cell 101, a digit voltage outputted from a selected memory cell 101 via the digit line 105, and a reference voltage outputted from the dummy cell 110 in the same row as the selected memory cell 101 via the dummy digit line 111 are inputted to the complementary level comparing sense amplifier and data write buffer combined circuit 112. The circuit 112 amplifies a difference between the reference voltage and the digit voltage and then outputs the amplified voltage via a data output terminal 1121. In this time, the circuit 112 compares the digit voltage with the reference voltage, and, if the digit voltage is higher, outputs the digit voltage as High level; on the other hand, if the digit voltage is lower, outputs it as Low level.
As described above, the semiconductor memory 100 having the memory cells 101 with the single-ended digit structure generates a reference voltage for data readout from the memory cell 101.
Since driver transistors 1102 of the dummy cells 110 have equal current capacity, the dummy cells 110 also have equal current capacity. Thus, each dummy cell 110 outputs a reference voltage of the same level. In other words, the semiconductor memory 100 generates a single reference level.
In data read operation in the semiconductor memory 100, high-speed data output is possible if the level of a reference voltage outputted from the dummy cell 110, which is a reference level, is a center voltage level between High and Low levels of a digit voltage outputted from the memory cell 101, which is referred to hereinafter simply as a center level.
However, a reference voltage in a finished chip can be different from a simulation result at the time of design. This is because the reference voltage varies from a desired value due to a variation in transistor capacity (the current capacity of the driver transistor 1102 in the dummy cell 110) and a variation in capacity of the dummy digit line 111. It is thereby difficult to obtain a reference voltage in a finished chip having a center level between High and Low levels of memory cell data (digit voltage). If the reference level is not the center level, a difference between the reference voltage and the digit voltage becomes undesirably small to cause degradation (delay) in data output time or access time.
Specifically, the reference level becomes higher than the center level if the transistor capacity of the dummy cell 110 is small or the capacity of the dummy digit line 111 is large. A difference between High level of the digit voltage and the reference level thereby becomes small, causing delay in output time of High level data. On the contrary, the reference level becomes lower than the center level if the transistor capacity of the dummy cell 110 is large or the capacity of the dummy digit line 111 is small. A difference between Low level of the digit voltage and the reference level thereby becomes small, causing delay in output time of Low level data.
The above problems are explained hereinbelow in detail with reference to FIG. 11 to 13.
FIGS. 11 to 13 show a change in waveform of a digit voltage D and a reference voltage RDD with time in data read operation. FIG. 11 shows the case where the reference level is a center level, FIG. 12, where it is higher than the center level, and FIG. 13, where it is lower than the center level.
The data read operation via the digit line 105 precharged with a precharge level (VDD voltage) during stand-by time (precharge period) starts in synchronization with the rise in the read word line 104.
The complementary level comparing sense amplifier and data write buffer combined circuit 112 compares the digit voltage D with the reference voltage RDD, and, if the digit voltage D is higher, outputs the digit voltage D as High level; if the digit voltage D is lower, outputs it as Low level, from the data output terminal 1121, as described above.
At the timing when a difference S between the digit voltage D and the reference voltage RDD reaches a predetermined level, memory cell data with High or Low level of the digit voltage D is outputted.
Thus, in the case where the reference level is the center level as shown in FIG. 11, an elapsed time until the difference S reaches a predetermined level is equal when the memory cell data is High and when it is Low, allowing the output timing of the memory cell data to be the same. It is thereby possible to operate with a desired access time just like the simulation.
However, in the case where the reference level is higher than the center level as shown in FIG. 12, an elapsed time until the difference S reaches a predetermined level is delayed when the memory cell data is High, causing a delay in data output timing.
On the other hand, in the case where the reference level is lower than the center level as shown in FIG. 13, an elapsed time until the difference S reaches a predetermined level is delayed when the memory cell data is Low, causing a delay in data output timing.
In this way, if the reference level is not the center level, output timing of High or Low level data is delayed, which hinders high-speed data output as simulated at the time of design.